Field of the Invention
Embodiments of the present invention relate generally to computer system power supply and, more specifically, to a technique for reducing voltage droop by throttling instruction issue rate.
Description of the Related Art
When a conventional computer chip is powered on, an instruction issue unit within the computer chip typically initiates processing by fetching instructions from memory and then issuing those instructions to execution units within the chip. When the execution units begin executing those instructions, the chip begins to draw increasing amounts of power from a power supply.
If the instruction issue unit issues a significant number of instructions over a short period of time, then the computer chip may suddenly draw an increased amount of current in order to power the execution units. In turn, the voltage provided by the power supply may suddenly decrease. This phenomenon is known in the art as “voltage droop.”
Voltage droop can be problematic because modern computer chips require at least a minimum amount of voltage in order to function properly. If the supply voltage droops below that minimum amount, then the computer chip may not operate with peak performance or, worse yet, may fail to operate entirely.
Accordingly, what is needed in the art is a technique for reducing the incidence of voltage droop in computer chips.